1. Field of the Invention
The present invention generally relates to ATM (Asynchronous Transfer Mode) exchanges, and more particularly to a control system for switching between duplicated switch units in an ATM exchange.
2. Description of the Prior Art
Recently, there has been considerable activity in the research of a B-ISDN (Broadband-Integrated Services Digital Network) as well as ATM exchanges used for such a B-ISDN. In order to attain high reliability, it is desirable to employ a redundant (duplicated) structure with respect to important parts of ATM exchanges.
In the ATM exchanges, switching is carried out for each cell. The duplicated structure has two systems, one of which is the active system, and the other of which is the standby system. If a fault has occurred in the duplicated structure, the standby system must immediate as the active system. In this case, it is desirable to perform the switching without any increase in the buffer capacity and complex control processing.
FIG. 1 is a block diagram of a conventional ATM exchange having a duplicated structure, and FIG. 2 is a block diagram of an ATM switch shown in FIG. 1.
Referring to FIG. 1, the ATM exchange comprises a transmission line interface 10, two switch units 11a and 11b, a selector 12, and a transmission line interface 13. A duplicated structure consists of the switch unit 11a serving as system #0, and the switch unit 11b serving as system #1. Each of the switch units 11a and 11b is made up of a multiplexer MUX, a switch SW, and a demultiplexer DMX.
One of the switch units 11a and 11b functions as the active system, and the other switch unit functions as the standby system. For example, the operation modes of the switch units 11a and 11b are periodically interchanged with each other. If a fault has occurred in the active system, the active system is switched to the standby system, while the standby system is switched to the active system. The above switchover is achieved by means of, for example, hardware.
It will now be assumed that the switch unit 11a is the active system and the switch unit 11b is the standby system. ATM cells transferred sequentially via the incoming transmission line are supplied to both the switch units 11a and 11b via the transmission line interface 10. During the above operation, the transmission line interface 10 receives an instruction signal from a control device (not shown for the sake of convenience), and writes a one-bit active-system indication bit into each ATM cell. For example, the active-system indication bit can be written into an ATM header of each ATM cell. According to the CCITT Recommendations I.361 and I.363, one ATM cell is a piece of 53-byte data, and consists of a 5-byte header and a 48-byte information field. In cases where routing information (route indication information) for switching is added to the ATM header of each ATM cell, the one-bit active-system indication bit is written into the routing information. For example, "1" is written, as the active-system indication bit, into each ATM cell output to the switch unit 11a, and "0" is written into each ATM cell output to the switch unit 11b.
The ATM cells with the active-system indication bit added thereto are switched in the switch units 11a and 11b, and are output to the selector 12. The selector 12 refers to the active-system indication bit in each ATM cell, and allows only the ATM cells from the active system (switch unit 11a in the example being considered) to pass through the selector 12. That is, the ATM cells having the active-system indication bit "1" are allowed to pass through the selector 12.
As has been described previously, the switching between the active system and the standby system is carried out periodically or carried out when a fault has occurred in the active system. In the example being considered, when a fault has occurred in the switch unit 11a, the switch unit 11a is switched to the standby system, and the switch unit 11b is switched to the active system under the control of the control device (not shown). The transmission line interface 10 writes the active-system indication bit "0" into each ATM cell output to the switch unit 11a, and writes the active-system indication bit "1" into each ATM cell output to the switch unit 11b. In this case, it is necessary for the selector 12 to select all ATM cells, each having the active-system indication bit "1", from the switch unit 11a which was previously the active system. After the above selection is completed, that is, all ATM cells, each having the active-system indication bit "1", from the switch unit 11a have been transferred to the transmission line interface 13, the selector 12 selects all ATM cells, each having the active-system indication bit "1", from the switch unit 11b which is the active system at present.
FIG. 2 shows the structure of the switch unit 11a shown in FIG. 1. The structure of the switch unit 11b is the same as that of the switch unit 11a, and is therefore omitted. The multiplexer (MUX) 110a comprises two multiplexers MUXI and MUX2. The switch (SW) 111a consists of three switching stages, each of which includes two SRMs (Self Routing Module), A and D, B and E, and C and F. Each of the SRMs at the first and second stages is connected to the two SRMs at the second and third stages, respectively. For example, the SRM A of the first stage is connected to the SRMs B and E of the second stage. Each of the SRMs has the switching function of directing each ATM cell to one of a plurality of outputs thereof (two outputs in the structure shown in FIG. 2) in accordance with the route indication information contained in the routing information and defined for each of the switching stages. The SRMs C and F of the third (final) stage are connected to demultiplexers DMX1 and DMX2 of the demultiplexer (DMX) 112a, respectively. The demultiplexers DMX1 and DMX2 are respectively connected to selectors (SEL1) 12A and (SEL2) 12B of the selector 12. The selectors 12A and 12B receive ATM cells from the switch unit 11b in the same manner as the above.
When the switch unit 11a is operating as the active system, each ATM cell input from the multiplexer 110a to the switch 111a has the active-system indication bit "1". Each ATM cell is subjected to the switching operation by means of the SRMs of the switch 111a, and is output to either the demultiplexer DMX1 or DMX2.
When the switching between the active system and the standby system is performed under the control of the control device, the active-system indication bit "0" is written into each ATM cell output to the switch 111a, and the active-system indication bit "1" is written into each ATM cell output to the other switch. The selectors 12A and 12B select all ATM cells which respectively have the active-system indication bit "1" and which are output from the switch 111a that was previously the active system. Further, the selectors 12A and 12B select all ATM cells which respectively have the active-system indication bit "1" and which are output from the other switch that is presently the active system after all the ATM cells respectively having the active-system indication bit "1" have been output from the switch 111a.
As has been described above, the conventional ATM exchange shown in FIGS. 1 and 2, the outputting of ATM cells output from the active system switched from the standby system is started after all the ATM cells remaining in the switch which was previously the active system have been read therefrom. Hence, it is necessary to hold the ATM cells in the active system which was previously switched from the standby system until all the ATM cells respectively having the active-system indication bit "1" have been read out from the other switch which was previously the active system. As a result, the switch units 11a and 11b have a large buffer (storage) capacity (particularly, the buffer capacity of the demultiplexers DMX1 and DMX2) used for temporarily holding the ATM cells.
In addition, the conventional ATM exchange has the following disadvantage. The demultiplexer DMX1 is connected to the SRM C, and therefore the demultiplexer DMX1 does not have information concerning the status (the available buffer capacity) of the SRM F. Hence, the demultiplexer DMX1 does not determine whether or not the SRM is completely empty. The above holds true for the demultiplexer DMX2, which does not have information converting the status of the SRM C. Hence, it is very difficult to determine the timing for switching in the selectors 12A and 12B. It is to be noted that the selectors 12A and 12B connected to the same demultiplexer (DMX) 112a must be concurrently switched.
Furthermore, it is necessary to define various control signals and provide devices for generating the control signals in order to achieve the above-mentioned switching between the active system and the standby system. For example, a control signal is needed to select only ATM cells respectively having the active-system indication bit "1" after switching. Further, it is necessary to use a control signal showing that all ATM cells respectively having the active-system indication bit "1" have been output from the switch unit which was the active system before switching.